1. Technical Field
The disclosure relates to serial communication interfaces, including conditioning techniques implemented on the signal to be transmitted at the physical layer.
2. Description of the Related Art
The transmission of a serial signal is subject to a number of constraints imposed by the various serial interface standards. Among these constraints, it is sought to ensure that the clock can be recovered from the signal by the receiver circuit, and that the signal has a DC component that varies little around zero (or around 50% of the signal excursion). In more recent interfaces, where rates can exceed one gigabit/s, the standards also require that the signal produces low electromagnetic interference. Electromagnetic compliance of the signal is acquired, for example, when the spectrum of the transmitted signal has no peak beyond the bounds of a template specified by the standard.
FIG. 1A illustrates conditioning operations performed at the physical layer for the USB 2.0 standard. These operations are intended to ensure clock recovery, however without guaranteeing the consistency of the DC component.
The raw serial signal D is subjected at 10 to a bit-stuffing operation. In general, bit-stuffing comprises inserting bits in the signal to create transitions where the raw signal has too few transitions to guarantee clock recovery. According to the USB 2.0 standard, this operation comprises inserting in the signal a 0-bit after any sequence of six 1-bits. The bits thus inserted are dummies in that they have no meaning—they are removed from the signal by the receiving circuit.
After the stuffing operation, the signal is subjected at 12 to an NRZI coding (“Non-Return to Zero Inverted”). This operation comprises encoding each 0-bit by a transition, and each 1-bit by a lack of transition.
FIG. 1B is a timing diagram illustrating an example of a raw serial signal D and the corresponding signals after the operations 10 and 12 (B-STUFF and NRZI).
Signal D conveys a synchronization word (seven 0-bits followed by one 1-bit), followed by an 8-bit sequence of 1-bits, then the sequence 0, 1, 0.
The stuffing operation inserts a 0-bit after the sixth 1-bit, identified by an arrow. This will ensure the presence of at least one transition for 6 consecutive 1-bits, but does not guarantee a transition in the sequence of 0-bits.
After the NRZI operation, the output signal Tx has a transition before each 0-bit, and has no transition before each 1-bit. This ensures a high number of transitions for the bit sequences of zeros.
The combination of the two operations ensures sufficient transitions in the output signal Tx for any series of consecutive bits of the same state (0 or 1) in the raw signal D.
These operations also tend to improve the consistency of the DC component of the Tx output signal, but do not guarantee a small margin of variation of the DC component.
More recent serial interface standards, aiming rates exceeding one gigabit/s, impose constraints that cannot be fulfilled by the technique of FIG. 1A, in particular relating to electromagnetic interference.
FIG. 2 illustrates conditioning operations performed at the physical layer for more recent high-speed serial transmission standards, such as HDMI, SATA, USB 3, PCI-Express (before version 3), Ethernet, FireWire, etc.
Raw serial signal D is subjected at 14 to a scrambling operation. This operation comprises mixing the incoming signal with a pseudo-random bit sequence, through a bitwise exclusive-OR operation. The pseudo-random sequence is generated by a linear feedback shift register (LFSR), hardwired according to a specific generator polynomial, G(x)=x16+x5+x4+x3+1 in the USB 3 standard. The original signal can be recovered in the receiving circuit by subjecting the scrambled signal to the same pseudo-random sequence.
Such a scrambling operation produces statistically a signal having random characteristics, thus having a flat spectrum and generating little EMI. But the scrambling does not guarantee that the scrambled signal has sufficient transitions for recovering the clock in all cases, and does not guarantee that the scrambled signal has a DC component of low variation in all cases.
To satisfy these two last constraints, the scrambled signal is subjected at 16 to a line coding operation, the 8b/10b coding for the standards listed above. Such coding replaces every byte of the scrambled signal with a 10-bit word sought in a lookup table. The 10-bit words are constructed so that each pair of successive 10-bit words in the output signal has a transition after at most 5 bits at the same state. Furthermore, each byte of the scrambled signal has two 10-bit candidates in the table, with different numbers of 1-bits. The one or the other candidate is selected based on the number of 1-bits in the previous word, so as to tend to balance the number of 1-bits and the number of 0-bits over a small number of consecutive words in the outgoing signal. Such a coding thus ensures sufficient transitions and, especially, a DC component having a small variation.
Signal conditioning techniques of the type of FIG. 2 provide satisfactory results, but the line coding consumes a portion of the available bandwidth on the physical link (8b/10b coding requires 25% more data) and requires storing a lookup table and a relatively complex processing.